GATE CSE Concept Authority Hub

Computer Organization and Architecture Solved GATE Questions

Understand pipeline hazard bubbles, cache hit mapping, instruction set ISA formats, and memory interleaving math.

Indexed Doubts 10 Questions
Core Syllabus Focus GATE & ISRO CS

Practice Questions (10)

NQuestions1060

Cache Memory Direct vs Set-Associative Mapping (Variation 10)

A computer has a main memory of 64 KB and a cache memory of 2 KB. The block size is 64 bytes. If the cache is designed as a 2-way set-associative c...

Asked by NileshNama Votes: 20 | Views: 530
NQuestions1059

Pipelining and Pipeline Hazards Speedup (Variation 9)

A non-pipelined processor takes 10 ns to execute an instruction. The same processor is designed as a 5-stage pipeline. The stages take 1.2 ns, 1.5 ns,...

Asked by Rahul_Mehta Votes: 19 | Views: 522
NQuestions1058

Cache Memory Direct vs Set-Associative Mapping (Variation 8)

A computer has a main memory of 64 KB and a cache memory of 2 KB. The block size is 64 bytes. If the cache is designed as a 2-way set-associative c...

Asked by Ananya_Sharma Votes: 18 | Views: 514
NQuestions1057

Pipelining and Pipeline Hazards Speedup (Variation 7)

A non-pipelined processor takes 10 ns to execute an instruction. The same processor is designed as a 5-stage pipeline. The stages take 1.2 ns, 1.5 ns,...

Asked by Kiran_Kumar Votes: 17 | Views: 506
NQuestions1056

Cache Memory Direct vs Set-Associative Mapping (Variation 6)

A computer has a main memory of 64 KB and a cache memory of 2 KB. The block size is 64 bytes. If the cache is designed as a 2-way set-associative c...

Asked by Pradyumna_Rao Votes: 16 | Views: 498
NQuestions1055

Pipelining and Pipeline Hazards Speedup (Variation 5)

A non-pipelined processor takes 10 ns to execute an instruction. The same processor is designed as a 5-stage pipeline. The stages take 1.2 ns, 1.5 ns,...

Asked by NileshNama Votes: 15 | Views: 490
NQuestions1054

Cache Memory Direct vs Set-Associative Mapping (Variation 4)

A computer has a main memory of 64 KB and a cache memory of 2 KB. The block size is 64 bytes. If the cache is designed as a 2-way set-associative c...

Asked by Rahul_Mehta Votes: 14 | Views: 482
NQuestions1053

Pipelining and Pipeline Hazards Speedup (Variation 3)

A non-pipelined processor takes 10 ns to execute an instruction. The same processor is designed as a 5-stage pipeline. The stages take 1.2 ns, 1.5 ns,...

Asked by Ananya_Sharma Votes: 13 | Views: 474
NQuestions1052

Cache Memory Direct vs Set-Associative Mapping

A computer has a main memory of 64 KB and a cache memory of 2 KB. The block size is 64 bytes. If the cache is designed as a 2-way set-associative c...

Asked by Kiran_Kumar Votes: 12 | Views: 466
NQuestions1051

Pipelining and Pipeline Hazards Speedup

A non-pipelined processor takes 10 ns to execute an instruction. The same processor is designed as a 5-stage pipeline. The stages take 1.2 ns, 1.5 ns,...

Asked by Pradyumna_Rao Votes: 11 | Views: 459

Explore Other GATE CSE Subjects

Theory of ComputationOperating SystemsComputer NetworksDatabase Management SystemsEngineering MathematicsDigital LogicData StructuresAlgorithmsCompiler Design